HEAD Lab

BenDan: Benchmarking DPU performance on FPGAs

Wed, 01 Jul 2026 00:00:00 +0000

FANE: FPGA-Based FP8 Approximate Neural Network Engine

Mon, 01 Jun 2026 00:00:00 +0000

Bruno da Silva visits Southeast University for education and research exchange

Thu, 28 May 2026 00:00:00 +0000

On May 28, 2026, Bruno da Silva visited the Electrical and Electronic Experiment Center at Southeast University at the invitation of Prof. Ming Ling, where he joined a dedicated education and teaching exchange seminar.

Prof. Ming Ling, director of the Electrical and Electronic Experiment Center, together with graduate student representatives from the School of Integrated Circuits, participated in the exchange and lab visit. Prof. Ling first introduced the center’s history, laboratory development, experimental course offerings, and recent teaching reform activities.

Bruno da Silva then introduced Vrije Universiteit Brussel (VUB), with a focus on the research directions, training programs, and recent research outcomes of the Electronics and Informatics Department (ETRO). During the open discussion, both sides explored potential collaboration in embedded-systems education, talent development, and scientific research.

Building on this visit, the two sides aim to further deepen teaching and research exchanges, continue exploring new models for innovative engineering education, and support the steady improvement of higher engineering education quality.

Bruno da Silva visits WCH headquarters for RISC-V lab collaboration

Thu, 28 May 2026 00:00:00 +0000

Bruno da Silva visited the WCH headquarters at the invitation of Dr. Yong Yang, CTO of WCH. During the visit, Dr. Yong Yang introduced WCH’s history, current development, and main product lines, and presented a series of demonstrations showcasing the company’s embedded and RISC-V technologies.

The visit also provided an opportunity for both sides to exchange updates on the course development progress for the WCH-ETRO Joint RISC-V Laboratory. The discussion focused on how to connect WCH’s industrial platforms and technical expertise with ETRO’s education and research activities in embedded systems.

At the end of the visit, Bruno da Silva appointed Dr. Yong Yang as a guest lecturer of VUB ETRO, further strengthening the collaboration between WCH and ETRO in RISC-V education and applied embedded-system innovation.

From Brussels to Shanghai: ETRO researchers present 2 papers at ISCAS 2026

Wed, 27 May 2026 00:00:00 +0000

Ruiqi Chen, Abdessamad Nassihi, and Bruno da Silva proudly represented ETRO at the International Symposium on Circuits and Systems (ISCAS 2026) in Shanghai, one of the leading conferences in the field of circuits and systems. They presented two major contributions pushing the boundaries of power-efficient edge computing.

Challenges of pulse oximetry in Ethiopian healthcare

Fri, 01 May 2026 00:00:00 +0000

Equicore: Accelerating Clebsch-Gordan Tensor Product of Equivariant Neural Networks on FPGA

Wed, 01 Apr 2026 00:00:00 +0000

FP8ApproxLib: An FPGA-based approximate multiplier library for 8-bit floating point

Wed, 01 Apr 2026 00:00:00 +0000

TrackGNN: A Highly Parallelized and Self-Adaptive GNN Accelerator for Track Reconstruction on FPGAs

Wed, 01 Apr 2026 00:00:00 +0000

Exploiting Low-Power Techniques of a Flash-Based SoC FPGA for Energy-Efficient Edge Processing

Sun, 01 Mar 2026 00:00:00 +0000

Dr. Yong Yang visits the VUB ETRO Embedded Lab

Fri, 28 Nov 2025 00:00:00 +0000

Dr. Yong Yang visited the VUB ETRO Embedded Lab and met with Bruno da Silva for an exchange on embedded systems research, education, and future collaboration opportunities.

During the visit, they held preliminary discussions on establishing a joint RISC-V laboratory between WCH and ETRO. The proposed collaboration aims to connect industrial RISC-V platforms with ETRO’s research and teaching activities in embedded computing, creating opportunities for joint experimentation, student training, and applied hardware-software innovation.

Gold Prize in the 2nd Global Digital Intelligence Education Innovation Competition

Sat, 01 Nov 2025 00:00:00 +0000

Our team won the Gold Prize (1st) in the AI for Science High-Performance Optimization group of the 2nd Global Digital Intelligence Education Innovation Competition.

The team was led by Shidi Tang, with team members Yuedong Zhang, Ankun Tian, and Ruiqi Chen. The advisors were Ming Ling, Bruno da Silva, and Yanxiang Zhu.

Diff-DiT: Temporal Differential Accelerator for Low-bit Diffusion Transformers on FPGA

Wed, 01 Oct 2025 00:00:00 +0000

FASE: An FPGA-Based Accelerator for Lightweight Sample Entropy With Monte Carlo Sampling

Fri, 01 Aug 2025 00:00:00 +0000

FPGA-based Approximate Multiplier for FP8

Thu, 01 May 2025 00:00:00 +0000

Bruno da Silva and Ruiqi Chen attend DATE'25 with an oral presentation on ATE-GCN

Wed, 02 Apr 2025 00:00:00 +0000

Bruno da Silva and Ruiqi Chen attended the 2025 Design, Automation and Test in Europe Conference (DATE'25), where Ruiqi delivered an oral presentation of ATE-GCN: An FPGA-Based Graph Convolutional Network Accelerator with Asymmetrical Ternary Quantization.

DATE is one of the top-tier conferences in electronic design automation (EDA), with nearly 2,000 submissions and an acceptance rate of only about 20% in 2025. This presentation marks the first DATE oral presentation from VUB ETRO with VUB as both the first affiliation and corresponding affiliation.

The paper introduces ATE-GCN, an FPGA-based accelerator for graph convolutional networks (GCNs). Existing ternary quantization can greatly simplify neural-network matrix multiplication, but the paper shows that applying conventional symmetric ternary quantization directly to GCNs can cause severe accuracy loss because GCN weights follow a bimodal distribution. ATE-GCN addresses this with an asymmetrical ternary quantization strategy tailored to GCN weights, together with a software-hardware co-optimized FPGA architecture. On the hardware side, ATE-GCN uses a unified processing-element array that supports both ternary computation and sparse matrix multiplication, while exploiting FPGA cascade structures and DSP resources for high throughput. Implemented on a Xilinx VCU118 FPGA board, the prototype keeps accuracy loss below 2%, achieves average speedups of 224.13x over CPU and 11.1x over GPU, and improves DSP efficiency by 63% compared with state-of-the-art FPGA-based GCN accelerators.

ATE-GCN: An FPGA-Based Graph Convolutional Network Accelerator with Asymmetrical Ternary Quantization

Sat, 01 Mar 2025 00:00:00 +0000

FPGA-Based Sparse Matrix Multiplication Accelerators: From State-of-the-Art to Future Opportunities

Fri, 01 Nov 2024 00:00:00 +0000

A taxonomy of low-power techniques in wearable medical devices for healthcare applications

Thu, 01 Aug 2024 00:00:00 +0000

Acceleration of fast sample entropy for FPGAs

Mon, 01 Jan 2024 00:00:00 +0000

AutoMLP: A Framework for the Acceleration of Multi-Layer Perceptron Models on FPGAs for Real-Time Atrial Fibrillation Disease Detection

Fri, 01 Dec 2023 00:00:00 +0000

Acceleration of Bucket-Assisted Fast Sample Entropy for Biomedical Signal Analysis

Fri, 01 Sep 2023 00:00:00 +0000

Acceleration of Fast Sample Entropy Towards Biomedical Applications on FPGAs

Thu, 01 Dec 2022 00:00:00 +0000

Evaluation of fast sample entropy algorithms on FPGAs: From performance to energy efficiency

Thu, 01 Sep 2022 00:00:00 +0000

Mon, 01 Jan 0001 00:00:00 +0000