<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>DATE 2025 | HEAD Lab</title><link>https://verimaketest.github.io/tag/date-2025/</link><atom:link href="https://verimaketest.github.io/tag/date-2025/index.xml" rel="self" type="application/rss+xml"/><description>DATE 2025</description><generator>Wowchemy (https://wowchemy.com)</generator><language>en-us</language><lastBuildDate>Wed, 02 Apr 2025 00:00:00 +0000</lastBuildDate><image><url>https://verimaketest.github.io/media/icon_hu0ab5c02c1f2ff27bbe76bf3235245d1a_922260_512x512_fill_lanczos_center_3.png</url><title>DATE 2025</title><link>https://verimaketest.github.io/tag/date-2025/</link></image><item><title>Bruno da Silva and Ruiqi Chen attend DATE'25 with an oral presentation on ATE-GCN</title><link>https://verimaketest.github.io/post/date-2025-ate-gcn-oral-presentation/</link><pubDate>Wed, 02 Apr 2025 00:00:00 +0000</pubDate><guid>https://verimaketest.github.io/post/date-2025-ate-gcn-oral-presentation/</guid><description>&lt;p>Bruno da Silva and Ruiqi Chen attended the 2025 Design, Automation and Test in Europe Conference (DATE'25), where Ruiqi delivered an oral presentation of &lt;a href="https://verimaketest.github.io/publication/chen-2025-ate/" target="_blank" rel="noopener">ATE-GCN: An FPGA-Based Graph Convolutional Network Accelerator with Asymmetrical Ternary Quantization&lt;/a>.&lt;/p>
&lt;p>DATE is one of the top-tier conferences in electronic design automation (EDA), with nearly 2,000 submissions and an acceptance rate of only about 20% in 2025. This presentation marks the first DATE oral presentation from VUB ETRO with VUB as both the first affiliation and corresponding affiliation.&lt;/p>
&lt;p>The paper introduces ATE-GCN, an FPGA-based accelerator for graph convolutional networks (GCNs). Existing ternary quantization can greatly simplify neural-network matrix multiplication, but the paper shows that applying conventional symmetric ternary quantization directly to GCNs can cause severe accuracy loss because GCN weights follow a bimodal distribution. ATE-GCN addresses this with an asymmetrical ternary quantization strategy tailored to GCN weights, together with a software-hardware co-optimized FPGA architecture. On the hardware side, ATE-GCN uses a unified processing-element array that supports both ternary computation and sparse matrix multiplication, while exploiting FPGA cascade structures and DSP resources for high throughput. Implemented on a Xilinx VCU118 FPGA board, the prototype keeps accuracy loss below 2%, achieves average speedups of 224.13x over CPU and 11.1x over GPU, and improves DSP efficiency by 63% compared with state-of-the-art FPGA-based GCN accelerators.&lt;/p></description></item></channel></rss>